FIG. 1 shows a prior art charge coupled device (CCD) operable in two modes. The first mode is a full-resolution image read out mode and the second mode is a half-resolution double speed read out mode. In the double speed read out mode, two adjacent charge packets are summed together and are transferred two times faster than in full resolution mode. These two modes allow for a two-dimensional pixel array to be read out in a full resolution still photography imaging mode and a reduced resolution video-imaging mode. Examples of this prior art can be found in patents U.S. Pat. Nos. 6,452,634 and 6,462,779.
In FIG. 1, a pseudo-2-phase CCD is shown with every other gate pair connected to timing signal H1. The gate pairs between H1 alternate between timing signals H2 and H3. FIG. 2 shows the timing signals for the full-resolution read out of FIG. 1. In full-resolution mode, H2 and H3 are clocked the same and with the opposite phase of H1. This timing causes the charge packets in the CCD to be advanced by two gate pairs for each clock cycle.
FIG. 3 shows the transfer of charge in the half-resolution double speed read out mode and FIG. 4 shows the timing signals for FIG. 3. H1 is held at a constant DC voltage. H2 and H3 are now clocked with opposite phase. The amplitude of the clock signals H2 and H3 is double the full-resolution mode amplitude shown in FIG. 2. This double speed timing advances the charge packets four gate pairs in one clock cycle, twice as far as the full-resolution mode. The double speed timing mode also sums together two adjacent charge packets to reduce the resolution by one half.
One deficiency of the charge transfer shown in FIG. 3 is the voltage potential steps are small and the distance the charge travels is long. Consequently, it is desirable to increase the voltage between adjacent gate pairs to increase the electric field strength in the CCD. An increased electric field will improve the charge transfer efficiency.